Download A Designer’s Guide to Built-In Self-Test by Charles E. Stroud PDF

By Charles E. Stroud

ISBN-10: 1402070500

ISBN-13: 9781402070501

A contemporary technological develop is the paintings of designing circuits to check themselves, known as a integrated Self-Test (BIST). this concept was once first proposed round 1980 and has grown to develop into some of the most very important checking out concepts on the present time, in addition to for the longer term. This e-book is written from a designer's point of view and describes the main BIST ways which were proposed and carried out for the reason that 1980, besides their benefits and obstacles. The BIST techniques comprise the integrated common sense Block Observer, pseudo-exhaustive BIST thoughts, round BIST, scan-based BIST, BIST for normal constructions, BIST for FPGAs and CPLDs, mixed-signal BIST, and the mixing of BIST with concurrent fault detection innovations for online trying out. specific awareness is paid to system-level use of BIST as a way to maximize some great benefits of BIST via lowered trying out time and price in addition to excessive diagnostic solution. the writer spent 15 years as a dressmaker at Bell Labs the place he designed over 20 construction VLSI units and three construction circuit forums. 16 of the VLSI units contained BIST of assorted forms for normal buildings and normal sequential good judgment, together with the 1st BIST for Random entry thoughts (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal platforms at Bell Labs. He has spent the previous 10 years in academia the place his examine and improvement keeps to target BIST, together with the 1st BIST for FPGAs and CPLDs in addition to persevered paintings within the zone of BIST for basic sequential good judgment and mixed-signal platforms. He holds 10 US patents (with five extra pending) for varied sorts of BIST ways. hence, the writer brings a special mix of data and adventure to this sensible consultant for designers, try out engineers, product engineers, procedure diagnosticians, and managers.

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Extra info for A Designer’s Guide to Built-In Self-Test

Sample text

An Overview of BIST cussed in Chapter 5). However, this example does illustrate the overall idea of a BIST architecture as well as the system-level operation of the approach. 3 Advantages and Disadvantages of BIST Given that BIST enables a circuit (VLSI device or PCB) to test itself, one of the main advantages of BIST is that it can easily be used at all levels of testing. This vertical testability, as it is often referred to, means that the same testing approach (BIST in this case) can be used at wafer and device-level testing, for all manufacturing testing, and even for system-level testing in the field.

The removal of equivalent faults while keeping one from each group for fault simulation is called fault collapsing [4]. On a 2-point signal net (with one source and one destination, or sink), the output of the source gate stuck-at-1 (stuck-at-0) cannot be distinguished from the input of the sink gate stuck-at-1 (stuck-at-0). Therefore, there are equivalent faults at the structural-level as well as at the gate-level. 7. The set of “collapsed” faults for each circuit is indicated in bold italics.

5c, the driver for one node “dominates” the driver for the other node; this is typically denoted as “A dom B” or “B dom A” depending on which driver is stronger. 5d for the wired-AND/OR and dominant bridging fault models where the differences in the faulty circuit from that of the fault-free circuit are highlighted in gray. Given two wires in a circuit, it is difficult to know which driver will be stronger or whether a short will behave as a wired-AND or a wired-OR. Therefore, both faults for a given fault model (wiredAND and wired-OR, or else, “A dom B” and “B dom A”) are emulated during fault simulation to determine if a given set of test vectors will detect both faults associated with that particular bridging fault model.

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